
adjacency-link:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400548 <_init>:
  400548:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40054c:	910003fd 	mov	x29, sp
  400550:	9400003a 	bl	400638 <call_weak_fn>
  400554:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400558:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400560 <.plt>:
  400560:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400564:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0x10014>
  400568:	f947fe11 	ldr	x17, [x16, #4088]
  40056c:	913fe210 	add	x16, x16, #0xff8
  400570:	d61f0220 	br	x17
  400574:	d503201f 	nop
  400578:	d503201f 	nop
  40057c:	d503201f 	nop

0000000000400580 <malloc@plt>:
  400580:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  400584:	f9400211 	ldr	x17, [x16]
  400588:	91000210 	add	x16, x16, #0x0
  40058c:	d61f0220 	br	x17

0000000000400590 <__libc_start_main@plt>:
  400590:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  400594:	f9400611 	ldr	x17, [x16, #8]
  400598:	91002210 	add	x16, x16, #0x8
  40059c:	d61f0220 	br	x17

00000000004005a0 <__gmon_start__@plt>:
  4005a0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005a4:	f9400a11 	ldr	x17, [x16, #16]
  4005a8:	91004210 	add	x16, x16, #0x10
  4005ac:	d61f0220 	br	x17

00000000004005b0 <abort@plt>:
  4005b0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005b4:	f9400e11 	ldr	x17, [x16, #24]
  4005b8:	91006210 	add	x16, x16, #0x18
  4005bc:	d61f0220 	br	x17

00000000004005c0 <__isoc99_scanf@plt>:
  4005c0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005c4:	f9401211 	ldr	x17, [x16, #32]
  4005c8:	91008210 	add	x16, x16, #0x20
  4005cc:	d61f0220 	br	x17

00000000004005d0 <printf@plt>:
  4005d0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005d4:	f9401611 	ldr	x17, [x16, #40]
  4005d8:	9100a210 	add	x16, x16, #0x28
  4005dc:	d61f0220 	br	x17

00000000004005e0 <putchar@plt>:
  4005e0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005e4:	f9401a11 	ldr	x17, [x16, #48]
  4005e8:	9100c210 	add	x16, x16, #0x30
  4005ec:	d61f0220 	br	x17

Disassembly of section .text:

00000000004005f0 <_start>:
  4005f0:	d280001d 	mov	x29, #0x0                   	// #0
  4005f4:	d280001e 	mov	x30, #0x0                   	// #0
  4005f8:	aa0003e5 	mov	x5, x0
  4005fc:	f94003e1 	ldr	x1, [sp]
  400600:	910023e2 	add	x2, sp, #0x8
  400604:	910003e6 	mov	x6, sp
  400608:	580000c0 	ldr	x0, 400620 <_start+0x30>
  40060c:	580000e3 	ldr	x3, 400628 <_start+0x38>
  400610:	58000104 	ldr	x4, 400630 <_start+0x40>
  400614:	97ffffdf 	bl	400590 <__libc_start_main@plt>
  400618:	97ffffe6 	bl	4005b0 <abort@plt>
  40061c:	00000000 	.inst	0x00000000 ; undefined
  400620:	00400eec 	.word	0x00400eec
  400624:	00000000 	.word	0x00000000
  400628:	00400f10 	.word	0x00400f10
  40062c:	00000000 	.word	0x00000000
  400630:	00400f90 	.word	0x00400f90
  400634:	00000000 	.word	0x00000000

0000000000400638 <call_weak_fn>:
  400638:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0x10014>
  40063c:	f947f000 	ldr	x0, [x0, #4064]
  400640:	b4000040 	cbz	x0, 400648 <call_weak_fn+0x10>
  400644:	17ffffd7 	b	4005a0 <__gmon_start__@plt>
  400648:	d65f03c0 	ret
  40064c:	00000000 	.inst	0x00000000 ; undefined

0000000000400650 <deregister_tm_clones>:
  400650:	d0000080 	adrp	x0, 412000 <malloc@GLIBC_2.17>
  400654:	91012000 	add	x0, x0, #0x48
  400658:	d0000081 	adrp	x1, 412000 <malloc@GLIBC_2.17>
  40065c:	91012021 	add	x1, x1, #0x48
  400660:	eb00003f 	cmp	x1, x0
  400664:	540000a0 	b.eq	400678 <deregister_tm_clones+0x28>  // b.none
  400668:	90000001 	adrp	x1, 400000 <_init-0x548>
  40066c:	f947d821 	ldr	x1, [x1, #4016]
  400670:	b4000041 	cbz	x1, 400678 <deregister_tm_clones+0x28>
  400674:	d61f0020 	br	x1
  400678:	d65f03c0 	ret
  40067c:	d503201f 	nop

0000000000400680 <register_tm_clones>:
  400680:	d0000080 	adrp	x0, 412000 <malloc@GLIBC_2.17>
  400684:	91012000 	add	x0, x0, #0x48
  400688:	d0000081 	adrp	x1, 412000 <malloc@GLIBC_2.17>
  40068c:	91012021 	add	x1, x1, #0x48
  400690:	cb000021 	sub	x1, x1, x0
  400694:	9343fc21 	asr	x1, x1, #3
  400698:	8b41fc21 	add	x1, x1, x1, lsr #63
  40069c:	9341fc21 	asr	x1, x1, #1
  4006a0:	b40000a1 	cbz	x1, 4006b4 <register_tm_clones+0x34>
  4006a4:	90000002 	adrp	x2, 400000 <_init-0x548>
  4006a8:	f947dc42 	ldr	x2, [x2, #4024]
  4006ac:	b4000042 	cbz	x2, 4006b4 <register_tm_clones+0x34>
  4006b0:	d61f0040 	br	x2
  4006b4:	d65f03c0 	ret

00000000004006b8 <__do_global_dtors_aux>:
  4006b8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006bc:	910003fd 	mov	x29, sp
  4006c0:	f9000bf3 	str	x19, [sp, #16]
  4006c4:	d0000093 	adrp	x19, 412000 <malloc@GLIBC_2.17>
  4006c8:	39412260 	ldrb	w0, [x19, #72]
  4006cc:	35000080 	cbnz	w0, 4006dc <__do_global_dtors_aux+0x24>
  4006d0:	97ffffe0 	bl	400650 <deregister_tm_clones>
  4006d4:	52800020 	mov	w0, #0x1                   	// #1
  4006d8:	39012260 	strb	w0, [x19, #72]
  4006dc:	f9400bf3 	ldr	x19, [sp, #16]
  4006e0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4006e4:	d65f03c0 	ret

00000000004006e8 <frame_dummy>:
  4006e8:	17ffffe6 	b	400680 <register_tm_clones>

00000000004006ec <undirected_graph>:
  4006ec:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  4006f0:	910003fd 	mov	x29, sp
  4006f4:	f9000fa0 	str	x0, [x29, #24]
  4006f8:	52800020 	mov	w0, #0x1                   	// #1
  4006fc:	b9002fa0 	str	w0, [x29, #44]
  400700:	14000011 	b	400744 <undirected_graph+0x58>
  400704:	b9402fa0 	ldr	w0, [x29, #44]
  400708:	b9402fa1 	ldr	w1, [x29, #44]
  40070c:	f9400fa2 	ldr	x2, [x29, #24]
  400710:	93407c00 	sxtw	x0, w0
  400714:	d37cec00 	lsl	x0, x0, #4
  400718:	8b000040 	add	x0, x2, x0
  40071c:	b9000001 	str	w1, [x0]
  400720:	b9402fa0 	ldr	w0, [x29, #44]
  400724:	f9400fa1 	ldr	x1, [x29, #24]
  400728:	93407c00 	sxtw	x0, w0
  40072c:	d37cec00 	lsl	x0, x0, #4
  400730:	8b000020 	add	x0, x1, x0
  400734:	f900041f 	str	xzr, [x0, #8]
  400738:	b9402fa0 	ldr	w0, [x29, #44]
  40073c:	11000400 	add	w0, w0, #0x1
  400740:	b9002fa0 	str	w0, [x29, #44]
  400744:	b9402fa0 	ldr	w0, [x29, #44]
  400748:	7100141f 	cmp	w0, #0x5
  40074c:	54fffdcd 	b.le	400704 <undirected_graph+0x18>
  400750:	52800020 	mov	w0, #0x1                   	// #1
  400754:	b9003fa0 	str	w0, [x29, #60]
  400758:	14000033 	b	400824 <undirected_graph+0x138>
  40075c:	9100a3a2 	add	x2, x29, #0x28
  400760:	9100b3a1 	add	x1, x29, #0x2c
  400764:	90000000 	adrp	x0, 400000 <_init-0x548>
  400768:	913f0000 	add	x0, x0, #0xfc0
  40076c:	97ffff95 	bl	4005c0 <__isoc99_scanf@plt>
  400770:	d2800200 	mov	x0, #0x10                  	// #16
  400774:	97ffff83 	bl	400580 <malloc@plt>
  400778:	f9001ba0 	str	x0, [x29, #48]
  40077c:	b9402ba1 	ldr	w1, [x29, #40]
  400780:	f9401ba0 	ldr	x0, [x29, #48]
  400784:	b9000001 	str	w1, [x0]
  400788:	b9402fa0 	ldr	w0, [x29, #44]
  40078c:	f9400fa1 	ldr	x1, [x29, #24]
  400790:	93407c00 	sxtw	x0, w0
  400794:	d37cec00 	lsl	x0, x0, #4
  400798:	8b000020 	add	x0, x1, x0
  40079c:	f9400401 	ldr	x1, [x0, #8]
  4007a0:	f9401ba0 	ldr	x0, [x29, #48]
  4007a4:	f9000401 	str	x1, [x0, #8]
  4007a8:	b9402fa0 	ldr	w0, [x29, #44]
  4007ac:	f9400fa1 	ldr	x1, [x29, #24]
  4007b0:	93407c00 	sxtw	x0, w0
  4007b4:	d37cec00 	lsl	x0, x0, #4
  4007b8:	8b000020 	add	x0, x1, x0
  4007bc:	f9401ba1 	ldr	x1, [x29, #48]
  4007c0:	f9000401 	str	x1, [x0, #8]
  4007c4:	d2800200 	mov	x0, #0x10                  	// #16
  4007c8:	97ffff6e 	bl	400580 <malloc@plt>
  4007cc:	f9001ba0 	str	x0, [x29, #48]
  4007d0:	b9402fa1 	ldr	w1, [x29, #44]
  4007d4:	f9401ba0 	ldr	x0, [x29, #48]
  4007d8:	b9000001 	str	w1, [x0]
  4007dc:	b9402ba0 	ldr	w0, [x29, #40]
  4007e0:	f9400fa1 	ldr	x1, [x29, #24]
  4007e4:	93407c00 	sxtw	x0, w0
  4007e8:	d37cec00 	lsl	x0, x0, #4
  4007ec:	8b000020 	add	x0, x1, x0
  4007f0:	f9400401 	ldr	x1, [x0, #8]
  4007f4:	f9401ba0 	ldr	x0, [x29, #48]
  4007f8:	f9000401 	str	x1, [x0, #8]
  4007fc:	b9402ba0 	ldr	w0, [x29, #40]
  400800:	f9400fa1 	ldr	x1, [x29, #24]
  400804:	93407c00 	sxtw	x0, w0
  400808:	d37cec00 	lsl	x0, x0, #4
  40080c:	8b000020 	add	x0, x1, x0
  400810:	f9401ba1 	ldr	x1, [x29, #48]
  400814:	f9000401 	str	x1, [x0, #8]
  400818:	b9403fa0 	ldr	w0, [x29, #60]
  40081c:	11000400 	add	w0, w0, #0x1
  400820:	b9003fa0 	str	w0, [x29, #60]
  400824:	b9403fa0 	ldr	w0, [x29, #60]
  400828:	7100401f 	cmp	w0, #0x10
  40082c:	54fff98d 	b.le	40075c <undirected_graph+0x70>
  400830:	d503201f 	nop
  400834:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400838:	d65f03c0 	ret

000000000040083c <directed_graph>:
  40083c:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400840:	910003fd 	mov	x29, sp
  400844:	f9000fa0 	str	x0, [x29, #24]
  400848:	52800020 	mov	w0, #0x1                   	// #1
  40084c:	b9002fa0 	str	w0, [x29, #44]
  400850:	14000011 	b	400894 <directed_graph+0x58>
  400854:	b9402fa0 	ldr	w0, [x29, #44]
  400858:	b9402fa1 	ldr	w1, [x29, #44]
  40085c:	f9400fa2 	ldr	x2, [x29, #24]
  400860:	93407c00 	sxtw	x0, w0
  400864:	d37cec00 	lsl	x0, x0, #4
  400868:	8b000040 	add	x0, x2, x0
  40086c:	b9000001 	str	w1, [x0]
  400870:	b9402fa0 	ldr	w0, [x29, #44]
  400874:	f9400fa1 	ldr	x1, [x29, #24]
  400878:	93407c00 	sxtw	x0, w0
  40087c:	d37cec00 	lsl	x0, x0, #4
  400880:	8b000020 	add	x0, x1, x0
  400884:	f900041f 	str	xzr, [x0, #8]
  400888:	b9402fa0 	ldr	w0, [x29, #44]
  40088c:	11000400 	add	w0, w0, #0x1
  400890:	b9002fa0 	str	w0, [x29, #44]
  400894:	b9402fa0 	ldr	w0, [x29, #44]
  400898:	7100141f 	cmp	w0, #0x5
  40089c:	54fffdcd 	b.le	400854 <directed_graph+0x18>
  4008a0:	52800020 	mov	w0, #0x1                   	// #1
  4008a4:	b9003fa0 	str	w0, [x29, #60]
  4008a8:	1400001e 	b	400920 <directed_graph+0xe4>
  4008ac:	9100a3a2 	add	x2, x29, #0x28
  4008b0:	9100b3a1 	add	x1, x29, #0x2c
  4008b4:	90000000 	adrp	x0, 400000 <_init-0x548>
  4008b8:	913f0000 	add	x0, x0, #0xfc0
  4008bc:	97ffff41 	bl	4005c0 <__isoc99_scanf@plt>
  4008c0:	d2800200 	mov	x0, #0x10                  	// #16
  4008c4:	97ffff2f 	bl	400580 <malloc@plt>
  4008c8:	f9001ba0 	str	x0, [x29, #48]
  4008cc:	b9402ba1 	ldr	w1, [x29, #40]
  4008d0:	f9401ba0 	ldr	x0, [x29, #48]
  4008d4:	b9000001 	str	w1, [x0]
  4008d8:	b9402fa0 	ldr	w0, [x29, #44]
  4008dc:	f9400fa1 	ldr	x1, [x29, #24]
  4008e0:	93407c00 	sxtw	x0, w0
  4008e4:	d37cec00 	lsl	x0, x0, #4
  4008e8:	8b000020 	add	x0, x1, x0
  4008ec:	f9400401 	ldr	x1, [x0, #8]
  4008f0:	f9401ba0 	ldr	x0, [x29, #48]
  4008f4:	f9000401 	str	x1, [x0, #8]
  4008f8:	b9402fa0 	ldr	w0, [x29, #44]
  4008fc:	f9400fa1 	ldr	x1, [x29, #24]
  400900:	93407c00 	sxtw	x0, w0
  400904:	d37cec00 	lsl	x0, x0, #4
  400908:	8b000020 	add	x0, x1, x0
  40090c:	f9401ba1 	ldr	x1, [x29, #48]
  400910:	f9000401 	str	x1, [x0, #8]
  400914:	b9403fa0 	ldr	w0, [x29, #60]
  400918:	11000400 	add	w0, w0, #0x1
  40091c:	b9003fa0 	str	w0, [x29, #60]
  400920:	b9403fa0 	ldr	w0, [x29, #60]
  400924:	7100401f 	cmp	w0, #0x10
  400928:	54fffc2d 	b.le	4008ac <directed_graph+0x70>
  40092c:	d503201f 	nop
  400930:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400934:	d65f03c0 	ret

0000000000400938 <mual>:
  400938:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  40093c:	910003fd 	mov	x29, sp
  400940:	f9000fa0 	str	x0, [x29, #24]
  400944:	52800020 	mov	w0, #0x1                   	// #1
  400948:	b9002fa0 	str	w0, [x29, #44]
  40094c:	1400000f 	b	400988 <mual+0x50>
  400950:	f9400fa1 	ldr	x1, [x29, #24]
  400954:	b9802fa0 	ldrsw	x0, [x29, #44]
  400958:	d37cec00 	lsl	x0, x0, #4
  40095c:	8b000020 	add	x0, x1, x0
  400960:	b9402fa1 	ldr	w1, [x29, #44]
  400964:	b9000001 	str	w1, [x0]
  400968:	f9400fa1 	ldr	x1, [x29, #24]
  40096c:	b9802fa0 	ldrsw	x0, [x29, #44]
  400970:	d37cec00 	lsl	x0, x0, #4
  400974:	8b000020 	add	x0, x1, x0
  400978:	f900041f 	str	xzr, [x0, #8]
  40097c:	b9402fa0 	ldr	w0, [x29, #44]
  400980:	11000400 	add	w0, w0, #0x1
  400984:	b9002fa0 	str	w0, [x29, #44]
  400988:	b9402fa0 	ldr	w0, [x29, #44]
  40098c:	7100141f 	cmp	w0, #0x5
  400990:	54fffe0d 	b.le	400950 <mual+0x18>
  400994:	d2800200 	mov	x0, #0x10                  	// #16
  400998:	97fffefa 	bl	400580 <malloc@plt>
  40099c:	f90013a0 	str	x0, [x29, #32]
  4009a0:	f94013a0 	ldr	x0, [x29, #32]
  4009a4:	52800081 	mov	w1, #0x4                   	// #4
  4009a8:	b9000001 	str	w1, [x0]
  4009ac:	f9400fa0 	ldr	x0, [x29, #24]
  4009b0:	f9400c01 	ldr	x1, [x0, #24]
  4009b4:	f94013a0 	ldr	x0, [x29, #32]
  4009b8:	f9000401 	str	x1, [x0, #8]
  4009bc:	f9400fa0 	ldr	x0, [x29, #24]
  4009c0:	f94013a1 	ldr	x1, [x29, #32]
  4009c4:	f9000c01 	str	x1, [x0, #24]
  4009c8:	d2800200 	mov	x0, #0x10                  	// #16
  4009cc:	97fffeed 	bl	400580 <malloc@plt>
  4009d0:	f90013a0 	str	x0, [x29, #32]
  4009d4:	f94013a0 	ldr	x0, [x29, #32]
  4009d8:	52800041 	mov	w1, #0x2                   	// #2
  4009dc:	b9000001 	str	w1, [x0]
  4009e0:	f9400fa0 	ldr	x0, [x29, #24]
  4009e4:	f9400c01 	ldr	x1, [x0, #24]
  4009e8:	f94013a0 	ldr	x0, [x29, #32]
  4009ec:	f9000401 	str	x1, [x0, #8]
  4009f0:	f9400fa0 	ldr	x0, [x29, #24]
  4009f4:	f94013a1 	ldr	x1, [x29, #32]
  4009f8:	f9000c01 	str	x1, [x0, #24]
  4009fc:	d2800200 	mov	x0, #0x10                  	// #16
  400a00:	97fffee0 	bl	400580 <malloc@plt>
  400a04:	f90013a0 	str	x0, [x29, #32]
  400a08:	f94013a0 	ldr	x0, [x29, #32]
  400a0c:	52800081 	mov	w1, #0x4                   	// #4
  400a10:	b9000001 	str	w1, [x0]
  400a14:	f9400fa0 	ldr	x0, [x29, #24]
  400a18:	f9401401 	ldr	x1, [x0, #40]
  400a1c:	f94013a0 	ldr	x0, [x29, #32]
  400a20:	f9000401 	str	x1, [x0, #8]
  400a24:	f9400fa0 	ldr	x0, [x29, #24]
  400a28:	f94013a1 	ldr	x1, [x29, #32]
  400a2c:	f9001401 	str	x1, [x0, #40]
  400a30:	d2800200 	mov	x0, #0x10                  	// #16
  400a34:	97fffed3 	bl	400580 <malloc@plt>
  400a38:	f90013a0 	str	x0, [x29, #32]
  400a3c:	f94013a0 	ldr	x0, [x29, #32]
  400a40:	52800061 	mov	w1, #0x3                   	// #3
  400a44:	b9000001 	str	w1, [x0]
  400a48:	f9400fa0 	ldr	x0, [x29, #24]
  400a4c:	f9401401 	ldr	x1, [x0, #40]
  400a50:	f94013a0 	ldr	x0, [x29, #32]
  400a54:	f9000401 	str	x1, [x0, #8]
  400a58:	f9400fa0 	ldr	x0, [x29, #24]
  400a5c:	f94013a1 	ldr	x1, [x29, #32]
  400a60:	f9001401 	str	x1, [x0, #40]
  400a64:	d2800200 	mov	x0, #0x10                  	// #16
  400a68:	97fffec6 	bl	400580 <malloc@plt>
  400a6c:	f90013a0 	str	x0, [x29, #32]
  400a70:	f94013a0 	ldr	x0, [x29, #32]
  400a74:	52800021 	mov	w1, #0x1                   	// #1
  400a78:	b9000001 	str	w1, [x0]
  400a7c:	f9400fa0 	ldr	x0, [x29, #24]
  400a80:	f9401401 	ldr	x1, [x0, #40]
  400a84:	f94013a0 	ldr	x0, [x29, #32]
  400a88:	f9000401 	str	x1, [x0, #8]
  400a8c:	f9400fa0 	ldr	x0, [x29, #24]
  400a90:	f94013a1 	ldr	x1, [x29, #32]
  400a94:	f9001401 	str	x1, [x0, #40]
  400a98:	d2800200 	mov	x0, #0x10                  	// #16
  400a9c:	97fffeb9 	bl	400580 <malloc@plt>
  400aa0:	f90013a0 	str	x0, [x29, #32]
  400aa4:	f94013a0 	ldr	x0, [x29, #32]
  400aa8:	52800081 	mov	w1, #0x4                   	// #4
  400aac:	b9000001 	str	w1, [x0]
  400ab0:	f9400fa0 	ldr	x0, [x29, #24]
  400ab4:	f9401c01 	ldr	x1, [x0, #56]
  400ab8:	f94013a0 	ldr	x0, [x29, #32]
  400abc:	f9000401 	str	x1, [x0, #8]
  400ac0:	f9400fa0 	ldr	x0, [x29, #24]
  400ac4:	f94013a1 	ldr	x1, [x29, #32]
  400ac8:	f9001c01 	str	x1, [x0, #56]
  400acc:	d2800200 	mov	x0, #0x10                  	// #16
  400ad0:	97fffeac 	bl	400580 <malloc@plt>
  400ad4:	f90013a0 	str	x0, [x29, #32]
  400ad8:	f94013a0 	ldr	x0, [x29, #32]
  400adc:	52800041 	mov	w1, #0x2                   	// #2
  400ae0:	b9000001 	str	w1, [x0]
  400ae4:	f9400fa0 	ldr	x0, [x29, #24]
  400ae8:	f9401c01 	ldr	x1, [x0, #56]
  400aec:	f94013a0 	ldr	x0, [x29, #32]
  400af0:	f9000401 	str	x1, [x0, #8]
  400af4:	f9400fa0 	ldr	x0, [x29, #24]
  400af8:	f94013a1 	ldr	x1, [x29, #32]
  400afc:	f9001c01 	str	x1, [x0, #56]
  400b00:	d2800200 	mov	x0, #0x10                  	// #16
  400b04:	97fffe9f 	bl	400580 <malloc@plt>
  400b08:	f90013a0 	str	x0, [x29, #32]
  400b0c:	f94013a0 	ldr	x0, [x29, #32]
  400b10:	52800061 	mov	w1, #0x3                   	// #3
  400b14:	b9000001 	str	w1, [x0]
  400b18:	f9400fa0 	ldr	x0, [x29, #24]
  400b1c:	f9402401 	ldr	x1, [x0, #72]
  400b20:	f94013a0 	ldr	x0, [x29, #32]
  400b24:	f9000401 	str	x1, [x0, #8]
  400b28:	f9400fa0 	ldr	x0, [x29, #24]
  400b2c:	f94013a1 	ldr	x1, [x29, #32]
  400b30:	f9002401 	str	x1, [x0, #72]
  400b34:	d2800200 	mov	x0, #0x10                  	// #16
  400b38:	97fffe92 	bl	400580 <malloc@plt>
  400b3c:	f90013a0 	str	x0, [x29, #32]
  400b40:	f94013a0 	ldr	x0, [x29, #32]
  400b44:	52800041 	mov	w1, #0x2                   	// #2
  400b48:	b9000001 	str	w1, [x0]
  400b4c:	f9400fa0 	ldr	x0, [x29, #24]
  400b50:	f9402401 	ldr	x1, [x0, #72]
  400b54:	f94013a0 	ldr	x0, [x29, #32]
  400b58:	f9000401 	str	x1, [x0, #8]
  400b5c:	f9400fa0 	ldr	x0, [x29, #24]
  400b60:	f94013a1 	ldr	x1, [x29, #32]
  400b64:	f9002401 	str	x1, [x0, #72]
  400b68:	d2800200 	mov	x0, #0x10                  	// #16
  400b6c:	97fffe85 	bl	400580 <malloc@plt>
  400b70:	f90013a0 	str	x0, [x29, #32]
  400b74:	f94013a0 	ldr	x0, [x29, #32]
  400b78:	52800021 	mov	w1, #0x1                   	// #1
  400b7c:	b9000001 	str	w1, [x0]
  400b80:	f9400fa0 	ldr	x0, [x29, #24]
  400b84:	f9402401 	ldr	x1, [x0, #72]
  400b88:	f94013a0 	ldr	x0, [x29, #32]
  400b8c:	f9000401 	str	x1, [x0, #8]
  400b90:	f9400fa0 	ldr	x0, [x29, #24]
  400b94:	f94013a1 	ldr	x1, [x29, #32]
  400b98:	f9002401 	str	x1, [x0, #72]
  400b9c:	d503201f 	nop
  400ba0:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400ba4:	d65f03c0 	ret

0000000000400ba8 <display>:
  400ba8:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400bac:	910003fd 	mov	x29, sp
  400bb0:	f9000fa0 	str	x0, [x29, #24]
  400bb4:	52800020 	mov	w0, #0x1                   	// #1
  400bb8:	b9002fa0 	str	w0, [x29, #44]
  400bbc:	1400001c 	b	400c2c <display+0x84>
  400bc0:	f9400fa1 	ldr	x1, [x29, #24]
  400bc4:	b9802fa0 	ldrsw	x0, [x29, #44]
  400bc8:	d37cec00 	lsl	x0, x0, #4
  400bcc:	8b000020 	add	x0, x1, x0
  400bd0:	f9400400 	ldr	x0, [x0, #8]
  400bd4:	f90013a0 	str	x0, [x29, #32]
  400bd8:	90000000 	adrp	x0, 400000 <_init-0x548>
  400bdc:	913f2000 	add	x0, x0, #0xfc8
  400be0:	b9402fa1 	ldr	w1, [x29, #44]
  400be4:	97fffe7b 	bl	4005d0 <printf@plt>
  400be8:	14000009 	b	400c0c <display+0x64>
  400bec:	f94013a0 	ldr	x0, [x29, #32]
  400bf0:	b9400001 	ldr	w1, [x0]
  400bf4:	90000000 	adrp	x0, 400000 <_init-0x548>
  400bf8:	913f6000 	add	x0, x0, #0xfd8
  400bfc:	97fffe75 	bl	4005d0 <printf@plt>
  400c00:	f94013a0 	ldr	x0, [x29, #32]
  400c04:	f9400400 	ldr	x0, [x0, #8]
  400c08:	f90013a0 	str	x0, [x29, #32]
  400c0c:	f94013a0 	ldr	x0, [x29, #32]
  400c10:	f100001f 	cmp	x0, #0x0
  400c14:	54fffec1 	b.ne	400bec <display+0x44>  // b.any
  400c18:	52800140 	mov	w0, #0xa                   	// #10
  400c1c:	97fffe71 	bl	4005e0 <putchar@plt>
  400c20:	b9402fa0 	ldr	w0, [x29, #44]
  400c24:	11000400 	add	w0, w0, #0x1
  400c28:	b9002fa0 	str	w0, [x29, #44]
  400c2c:	b9402fa0 	ldr	w0, [x29, #44]
  400c30:	7100141f 	cmp	w0, #0x5
  400c34:	54fffc6d 	b.le	400bc0 <display+0x18>
  400c38:	d503201f 	nop
  400c3c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400c40:	d65f03c0 	ret

0000000000400c44 <undirected_quan_graph>:
  400c44:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400c48:	910003fd 	mov	x29, sp
  400c4c:	f9000fa0 	str	x0, [x29, #24]
  400c50:	52800020 	mov	w0, #0x1                   	// #1
  400c54:	b9002fa0 	str	w0, [x29, #44]
  400c58:	14000017 	b	400cb4 <undirected_quan_graph+0x70>
  400c5c:	b9402fa0 	ldr	w0, [x29, #44]
  400c60:	b9402fa1 	ldr	w1, [x29, #44]
  400c64:	f9400fa2 	ldr	x2, [x29, #24]
  400c68:	93407c00 	sxtw	x0, w0
  400c6c:	d37cec00 	lsl	x0, x0, #4
  400c70:	8b000040 	add	x0, x2, x0
  400c74:	b9000001 	str	w1, [x0]
  400c78:	b9402fa0 	ldr	w0, [x29, #44]
  400c7c:	f9400fa1 	ldr	x1, [x29, #24]
  400c80:	93407c00 	sxtw	x0, w0
  400c84:	d37cec00 	lsl	x0, x0, #4
  400c88:	8b000020 	add	x0, x1, x0
  400c8c:	b900041f 	str	wzr, [x0, #4]
  400c90:	b9402fa0 	ldr	w0, [x29, #44]
  400c94:	f9400fa1 	ldr	x1, [x29, #24]
  400c98:	93407c00 	sxtw	x0, w0
  400c9c:	d37cec00 	lsl	x0, x0, #4
  400ca0:	8b000020 	add	x0, x1, x0
  400ca4:	f900041f 	str	xzr, [x0, #8]
  400ca8:	b9402fa0 	ldr	w0, [x29, #44]
  400cac:	11000400 	add	w0, w0, #0x1
  400cb0:	b9002fa0 	str	w0, [x29, #44]
  400cb4:	b9402fa0 	ldr	w0, [x29, #44]
  400cb8:	7100141f 	cmp	w0, #0x5
  400cbc:	54fffd0d 	b.le	400c5c <undirected_quan_graph+0x18>
  400cc0:	52800020 	mov	w0, #0x1                   	// #1
  400cc4:	b9003fa0 	str	w0, [x29, #60]
  400cc8:	1400003a 	b	400db0 <undirected_quan_graph+0x16c>
  400ccc:	910093a3 	add	x3, x29, #0x24
  400cd0:	9100a3a2 	add	x2, x29, #0x28
  400cd4:	9100b3a1 	add	x1, x29, #0x2c
  400cd8:	90000000 	adrp	x0, 400000 <_init-0x548>
  400cdc:	913f8000 	add	x0, x0, #0xfe0
  400ce0:	97fffe38 	bl	4005c0 <__isoc99_scanf@plt>
  400ce4:	d2800200 	mov	x0, #0x10                  	// #16
  400ce8:	97fffe26 	bl	400580 <malloc@plt>
  400cec:	f9001ba0 	str	x0, [x29, #48]
  400cf0:	b9402ba1 	ldr	w1, [x29, #40]
  400cf4:	f9401ba0 	ldr	x0, [x29, #48]
  400cf8:	b9000001 	str	w1, [x0]
  400cfc:	b94027a1 	ldr	w1, [x29, #36]
  400d00:	f9401ba0 	ldr	x0, [x29, #48]
  400d04:	b9000401 	str	w1, [x0, #4]
  400d08:	b9402fa0 	ldr	w0, [x29, #44]
  400d0c:	f9400fa1 	ldr	x1, [x29, #24]
  400d10:	93407c00 	sxtw	x0, w0
  400d14:	d37cec00 	lsl	x0, x0, #4
  400d18:	8b000020 	add	x0, x1, x0
  400d1c:	f9400401 	ldr	x1, [x0, #8]
  400d20:	f9401ba0 	ldr	x0, [x29, #48]
  400d24:	f9000401 	str	x1, [x0, #8]
  400d28:	b9402fa0 	ldr	w0, [x29, #44]
  400d2c:	f9400fa1 	ldr	x1, [x29, #24]
  400d30:	93407c00 	sxtw	x0, w0
  400d34:	d37cec00 	lsl	x0, x0, #4
  400d38:	8b000020 	add	x0, x1, x0
  400d3c:	f9401ba1 	ldr	x1, [x29, #48]
  400d40:	f9000401 	str	x1, [x0, #8]
  400d44:	d2800200 	mov	x0, #0x10                  	// #16
  400d48:	97fffe0e 	bl	400580 <malloc@plt>
  400d4c:	f9001ba0 	str	x0, [x29, #48]
  400d50:	b9402fa1 	ldr	w1, [x29, #44]
  400d54:	f9401ba0 	ldr	x0, [x29, #48]
  400d58:	b9000001 	str	w1, [x0]
  400d5c:	b94027a1 	ldr	w1, [x29, #36]
  400d60:	f9401ba0 	ldr	x0, [x29, #48]
  400d64:	b9000401 	str	w1, [x0, #4]
  400d68:	b9402ba0 	ldr	w0, [x29, #40]
  400d6c:	f9400fa1 	ldr	x1, [x29, #24]
  400d70:	93407c00 	sxtw	x0, w0
  400d74:	d37cec00 	lsl	x0, x0, #4
  400d78:	8b000020 	add	x0, x1, x0
  400d7c:	f9400401 	ldr	x1, [x0, #8]
  400d80:	f9401ba0 	ldr	x0, [x29, #48]
  400d84:	f9000401 	str	x1, [x0, #8]
  400d88:	b9402ba0 	ldr	w0, [x29, #40]
  400d8c:	f9400fa1 	ldr	x1, [x29, #24]
  400d90:	93407c00 	sxtw	x0, w0
  400d94:	d37cec00 	lsl	x0, x0, #4
  400d98:	8b000020 	add	x0, x1, x0
  400d9c:	f9401ba1 	ldr	x1, [x29, #48]
  400da0:	f9000401 	str	x1, [x0, #8]
  400da4:	b9403fa0 	ldr	w0, [x29, #60]
  400da8:	11000400 	add	w0, w0, #0x1
  400dac:	b9003fa0 	str	w0, [x29, #60]
  400db0:	b9403fa0 	ldr	w0, [x29, #60]
  400db4:	7100401f 	cmp	w0, #0x10
  400db8:	54fff8ad 	b.le	400ccc <undirected_quan_graph+0x88>
  400dbc:	d503201f 	nop
  400dc0:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400dc4:	d65f03c0 	ret

0000000000400dc8 <directed_quan_graph>:
  400dc8:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400dcc:	910003fd 	mov	x29, sp
  400dd0:	f9000fa0 	str	x0, [x29, #24]
  400dd4:	52800020 	mov	w0, #0x1                   	// #1
  400dd8:	b9002fa0 	str	w0, [x29, #44]
  400ddc:	14000017 	b	400e38 <directed_quan_graph+0x70>
  400de0:	b9402fa0 	ldr	w0, [x29, #44]
  400de4:	b9402fa1 	ldr	w1, [x29, #44]
  400de8:	f9400fa2 	ldr	x2, [x29, #24]
  400dec:	93407c00 	sxtw	x0, w0
  400df0:	d37cec00 	lsl	x0, x0, #4
  400df4:	8b000040 	add	x0, x2, x0
  400df8:	b9000001 	str	w1, [x0]
  400dfc:	b9402fa0 	ldr	w0, [x29, #44]
  400e00:	f9400fa1 	ldr	x1, [x29, #24]
  400e04:	93407c00 	sxtw	x0, w0
  400e08:	d37cec00 	lsl	x0, x0, #4
  400e0c:	8b000020 	add	x0, x1, x0
  400e10:	b900041f 	str	wzr, [x0, #4]
  400e14:	b9402fa0 	ldr	w0, [x29, #44]
  400e18:	f9400fa1 	ldr	x1, [x29, #24]
  400e1c:	93407c00 	sxtw	x0, w0
  400e20:	d37cec00 	lsl	x0, x0, #4
  400e24:	8b000020 	add	x0, x1, x0
  400e28:	f900041f 	str	xzr, [x0, #8]
  400e2c:	b9402fa0 	ldr	w0, [x29, #44]
  400e30:	11000400 	add	w0, w0, #0x1
  400e34:	b9002fa0 	str	w0, [x29, #44]
  400e38:	b9402fa0 	ldr	w0, [x29, #44]
  400e3c:	7100141f 	cmp	w0, #0x5
  400e40:	54fffd0d 	b.le	400de0 <directed_quan_graph+0x18>
  400e44:	52800020 	mov	w0, #0x1                   	// #1
  400e48:	b9003fa0 	str	w0, [x29, #60]
  400e4c:	14000022 	b	400ed4 <directed_quan_graph+0x10c>
  400e50:	910093a3 	add	x3, x29, #0x24
  400e54:	9100a3a2 	add	x2, x29, #0x28
  400e58:	9100b3a1 	add	x1, x29, #0x2c
  400e5c:	90000000 	adrp	x0, 400000 <_init-0x548>
  400e60:	913f8000 	add	x0, x0, #0xfe0
  400e64:	97fffdd7 	bl	4005c0 <__isoc99_scanf@plt>
  400e68:	d2800200 	mov	x0, #0x10                  	// #16
  400e6c:	97fffdc5 	bl	400580 <malloc@plt>
  400e70:	f9001ba0 	str	x0, [x29, #48]
  400e74:	b9402ba1 	ldr	w1, [x29, #40]
  400e78:	f9401ba0 	ldr	x0, [x29, #48]
  400e7c:	b9000001 	str	w1, [x0]
  400e80:	b94027a1 	ldr	w1, [x29, #36]
  400e84:	f9401ba0 	ldr	x0, [x29, #48]
  400e88:	b9000401 	str	w1, [x0, #4]
  400e8c:	b9402fa0 	ldr	w0, [x29, #44]
  400e90:	f9400fa1 	ldr	x1, [x29, #24]
  400e94:	93407c00 	sxtw	x0, w0
  400e98:	d37cec00 	lsl	x0, x0, #4
  400e9c:	8b000020 	add	x0, x1, x0
  400ea0:	f9400401 	ldr	x1, [x0, #8]
  400ea4:	f9401ba0 	ldr	x0, [x29, #48]
  400ea8:	f9000401 	str	x1, [x0, #8]
  400eac:	b9402fa0 	ldr	w0, [x29, #44]
  400eb0:	f9400fa1 	ldr	x1, [x29, #24]
  400eb4:	93407c00 	sxtw	x0, w0
  400eb8:	d37cec00 	lsl	x0, x0, #4
  400ebc:	8b000020 	add	x0, x1, x0
  400ec0:	f9401ba1 	ldr	x1, [x29, #48]
  400ec4:	f9000401 	str	x1, [x0, #8]
  400ec8:	b9403fa0 	ldr	w0, [x29, #60]
  400ecc:	11000400 	add	w0, w0, #0x1
  400ed0:	b9003fa0 	str	w0, [x29, #60]
  400ed4:	b9403fa0 	ldr	w0, [x29, #60]
  400ed8:	7100401f 	cmp	w0, #0x10
  400edc:	54fffbad 	b.le	400e50 <directed_quan_graph+0x88>
  400ee0:	d503201f 	nop
  400ee4:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400ee8:	d65f03c0 	ret

0000000000400eec <main>:
  400eec:	a9b37bfd 	stp	x29, x30, [sp, #-208]!
  400ef0:	910003fd 	mov	x29, sp
  400ef4:	910043a0 	add	x0, x29, #0x10
  400ef8:	97ffff53 	bl	400c44 <undirected_quan_graph>
  400efc:	9101c3a0 	add	x0, x29, #0x70
  400f00:	97ffff2a 	bl	400ba8 <display>
  400f04:	52800000 	mov	w0, #0x0                   	// #0
  400f08:	a8cd7bfd 	ldp	x29, x30, [sp], #208
  400f0c:	d65f03c0 	ret

0000000000400f10 <__libc_csu_init>:
  400f10:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400f14:	910003fd 	mov	x29, sp
  400f18:	a901d7f4 	stp	x20, x21, [sp, #24]
  400f1c:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0x10014>
  400f20:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0x10014>
  400f24:	91374294 	add	x20, x20, #0xdd0
  400f28:	913722b5 	add	x21, x21, #0xdc8
  400f2c:	a902dff6 	stp	x22, x23, [sp, #40]
  400f30:	cb150294 	sub	x20, x20, x21
  400f34:	f9001ff8 	str	x24, [sp, #56]
  400f38:	2a0003f6 	mov	w22, w0
  400f3c:	aa0103f7 	mov	x23, x1
  400f40:	9343fe94 	asr	x20, x20, #3
  400f44:	aa0203f8 	mov	x24, x2
  400f48:	97fffd80 	bl	400548 <_init>
  400f4c:	b4000194 	cbz	x20, 400f7c <__libc_csu_init+0x6c>
  400f50:	f9000bb3 	str	x19, [x29, #16]
  400f54:	d2800013 	mov	x19, #0x0                   	// #0
  400f58:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400f5c:	aa1803e2 	mov	x2, x24
  400f60:	aa1703e1 	mov	x1, x23
  400f64:	2a1603e0 	mov	w0, w22
  400f68:	91000673 	add	x19, x19, #0x1
  400f6c:	d63f0060 	blr	x3
  400f70:	eb13029f 	cmp	x20, x19
  400f74:	54ffff21 	b.ne	400f58 <__libc_csu_init+0x48>  // b.any
  400f78:	f9400bb3 	ldr	x19, [x29, #16]
  400f7c:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400f80:	a942dff6 	ldp	x22, x23, [sp, #40]
  400f84:	f9401ff8 	ldr	x24, [sp, #56]
  400f88:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400f8c:	d65f03c0 	ret

0000000000400f90 <__libc_csu_fini>:
  400f90:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400f94 <_fini>:
  400f94:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400f98:	910003fd 	mov	x29, sp
  400f9c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400fa0:	d65f03c0 	ret
